The present invention relates to a semiconductor memory device fabricated on a semicondutor substrate.
Memory capacity of semiconductor memory devices have been increased remarkably according to the improvement in fine patterning technique in the semiconductor field. In a semiconductor memory, a plurality of memory cells are arranged in a matrix form of rows and columns, and such a matrix of memory cells are usually divided into two or more memory arrays. Each of the rows and each of the columns are designated by row address signals and column address signals, respectively in the matrix.
However, accompanied by reduction in patterns of circuit elements and increase in the memory capacity, control of the respective manufacturing steps has become critical and difficult and deviation or fluctuations in the respective circuit elements have become large and innegligible. For example, for the same circuit elements such as memory cells, there is deviation in characteristics among them according to their locations even they are formed on the same chip. Particularly, deviations of characteristics in memory cells in the same chip are determinant factor in the memory device. Namely, a read out signal from a memory cell is generally very small and a margin in a signal stored in a memory cell is also small, and therefore the deviation of the characteristics in memory cells are required to be within a predetermined range. Otherwise, one of the binary data stored in a certain memory cell is erroneously read out of sensed as the other of the binary data, resulting in a mulfunction. Therefore, it is desirable that the memory cells included in the same chip have the same characteristics with no deviation among them.
In general, it has been considered that comparative errors in sizes or dimensions in circuit elements formed in the same semiconductor chip are very small for the same kind of circuit elements irrespective of their respective locations. For example, a field effect transistor with a channel length "k" and a field effect transistor with a channel length "nk" (n being a positive integer) are accurately formed on the same semiconductor chip with ease. However, the inventor of the present invention has found the fact that memory cells at the peripheral portion of the memory cell array are generally inferior to the memory cells at the internal portion of the memory cell array in the electrical characteristics. Namely, each memory cell at the internal portion of the memory cell array is necessarily surrounded by other memory cells and therefore the memory cells at the internal portion of the memory array are subjected to the same process atmosphere. While, each memory cell at the peripheral portion of the memory cell array is not surrounded by other memory cells but in adjacent to other regions such as an isolation region or other elements. Therefore, the affection of process to the memory cells at the peripheral portion of the memory cell array is not uniform over the entire memory cells at the peripheral portion of the memory cell array.
Thus, the uniformity in formation of the memory cells at the peripheral portion of the memory cell array is lower that that in the memory cells at the internal portion of the memory cell array and the memory cells at the peripheral portion of the array determines the worst characteristics of the memory cell in the array.